FIG. 1 shows a high-level block diagram of the layout of a conventional FPGA 100 having a logic core 102 surrounded (i.e., on one or more sides) by an input/output (I/O) ring 104. Logic core 102 includes an array of programmable logic blocks (PLBs) 106 intersected by rows of block memory 108. Each PLB contains circuitry that can be programmed to perform a variety of different functions. The memory blocks in each row are available to store data to be input to the PLBs and/or data generated by the PLBs. I/O ring 104 includes sets of programmable I/O buffers (PIBs) 110 programmably connected to the logic core by multiplexor/demultiplexor (mux/demux) circuits 112. The I/O buffers support external interfacing to FPGA 100. Also located within the I/O ring are a number of phase-locked loop (PLL) circuits 114 that are capable of providing different timing (i.e., clock) signals for use by the various elements within FPGA 100. Those skilled in the art will understand that FPGAs, such as FPGA 100, will typically include other elements, such as configuration memory, that are not shown in the high-level block diagram of FIG. 1. In addition, general routing resources, including clocks, buses, general-purpose routing, high-speed routing, etc. (also not shown in FIG. 1), are provided throughout the FPGA layout to programmably interconnect the various elements within FPGA 100.
The layout of a typical FPGA, such as FPGA 100 of FIG. 1, comprises multiple instances of a limited number of different types of blocks of circuitry. For example, an I/O ring may contain a number of instances of the same basic block of circuitry repeated around the periphery of the device. In the example of FPGA 100, I/O ring 104 is made up of multiple instances of the same basic programmable I/O circuit (PIC), where each PIC provides a particular number of the I/O buffers of the I/O ring. U.S. Pat. No. 6,472,904 B2 (“the '904 patent”), the teachings of which are incorporated herein by reference, provides a detailed description of an exemplary programmable I/O buffer of the prior art.
The rates of signals to be handled by FPGAs and other PLDs, and therefore the speeds at which I/O interfaces for such devices need to operate, exceed the current speed capabilities of the internal elements (e.g., the programmable logic blocks in the logic core) of these devices. In order to support such applications, I/O interfaces are designed to support demultiplexing of individual, incoming, high-rate signals into multiple, lower-rate signals that are then processed in parallel by the device's core logic. Similarly, I/O interfaces are designed to support multiplexing of multiple, low-rate signals into individual, higher-rate, outgoing signals. Nevertheless, individual prior-art I/O interfaces are still limited in the variety of muxing/demuxing schemes that they can support.